The Prior Art
Due to continuing miniaturization of integrated MOS circuits, transistors having channel lengths less than 1.5 .mu.m are required which operate with the standard voltage of 5 volts (-2.5 volts substrate voltage). The poor reproducibility of the threshold voltage represents a difficult technical problem. This is because of fluctuations in channel length or insufficient voltage stability as the result of avalanche multiplication, especially when coupled with a bipolar effect.
It is known from the prior art, for example the article by R. H. Dennard et al "Design of Ion-Implanted MOSFET's With Very Small Physical Dimensions" in IEEE Solid State Circuits, Vol. SC-9, pp. 256 through 268, 1974, to resolve this problem by using a MOS transistor constructed on a high-resistant substrate which receives a double implantation in the channel region and exhibits reduced source/drain penetration depths as well as a thin gate oxide.
The idea of double implantation in the channel region, for example, in a publication by P. P. Wang, in the IEEE, ED-24 (1977), pp. 196 through 204, is not fully exploited in practice. Specifically, a far smaller dose is selected for the deep implantation than would be optimum for shielding the drain voltage from the source, so as not to reduce the turnover voltage stability of the transistor.
Other ideas, such as double-implanted MOS structures, double-diffused MOS structures, MOS structures with buried zones, MOS structures with separate gates and weakly doped drain zones are likewise known for resolving the problem, but involve greater complexity and poorer reproducibility of the long channel threshold voltage as disadvantages.